This invention relates generally to electronic circuits and more particularly to buffers used in digital electronic circuits.
Digital electronic circuitry and, more particularly, highly integrated digital electronic circuitry is becoming faster, more complex, and more powerful with each succeeding generation. In very high speed digital circuitry, the ability to send signals between integrated circuit chips becomes limited by the capacitances and inductances of the leads and traces interconnecting the chips which can create noise and degrade performance. In consequence, the design of input/output (I/O) circuits becomes quite critical for high performance digital electronic circuits.
The digital buffer is an I/O circuit often used in digital electronic circuitry. Such buffers have low input capacitances, are capable of driving high capacitive loads and are characterized by signal propagation delays corresponding to the speed at which signals at their outputs can change in response to changes in signals at their inputs. With high performance digital circuitry it is desirable to have very high speed buffers, i.e. buffers which exhibit a minimum of signal propagation delay.
Another important consideration in the design of digital electronic circuitry is power consumption. In fact, a major limiting factor in the density of integrated digital circuits is the amount of power consumed by the circuitry and, therefore, the amount of heat generated by the circuitry.
It is well known that the use of Complementary Metal Oxide Semiconductor (CMOS) technology which pairs n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) with p-channel MOSFETS reduces power consumption in digital circuitry when compared with similar circuitry implemented solely in n-channel or p-channel MOSFETS. However, even CMOS devices consume appreciable power and, therefore, additional methods must be utilized to further reduce power consumption in digital circuitry.
There are generally two kinds of power loss within a digital electronic circuit. Static power loss is independent of the frequency of operation of the circuit and is essentially equal to I.sub.bias .times.V.sub.dd. Dynamic power loss is frequency related and is equal to CV.sup.2 f, where C is the total capacitance, V is the voltage level, and f is the frequency of operation of the digital circuit. The total power is the sum of the static power and the dynamic power.
Since both static and dynamic power are directly related to the voltage level, one way to reduce power consumption is to reduce the operating voltage of the digital circuitry. Standard CMOS logic levels range from zero volts d.c. (ground) to approximately five volts d.c. It is therefore possible to reduce power consumption and increase the speed of operation of a digital circuit by reducing the signal levels below five volts for portions of the circuit which are required to drive high capacitive loads.